1. Field of the Invention
The present invention relates to a despreading circuit of a receiver of a spread spectrum communication system such as mobile communication, radio LAN and the like, particularly to a simple despreading circuit which can reduce power consumption.
2. Description of the Related Art
In a spread spectrum communication system, in general, transmission data is narrow-band modulated (primary modulation) on a transmission side, and narrow-band modulated transmission data is further spread/modulated (secondary modulation), and the data subjected to the two-stage modulation is transmitted/outputted. Received data is despread on a reception side to extract the narrow-band modulated data, and a base band signal is regenerated in an ordinary wave detection circuit.
A conventional despreading circuit will be described with reference to FIG. 11. FIG. 11 is a block diagram of the conventional despreading circuit.
In the conventional despreading circuit, a sliding correlator constituted of a logic circuit is used, which performs capture in synchronization with a symbol break point and computes correlation in a synchronized phase.
Specifically, as shown in FIG. 11, the conventional sliding correlator is constituted of A/D converter 1, multiplier 2, PN code register 3, adder 4, and delay element 5.
Each section will be described hereinafter in detail. The A/D converter 1 receives a CDMA modulated analog signal, and converts the signal to a digital signal to output the signal.
The multiplier 2 multiplies and outputs PN code transmitted from the PN code register 3 and the signal transmitted from the A/D converter 1 for each chip.
The PN code register 3 transmits PN code (pseudo noise code) as a spread code to the multiplier 2.
Since one symbol is generally spread with a plurality of bits, the PN code has a multi-bit length, and the bit length is called the number of chips.
Additionally, a timing of PN code register 3 to output the PN code is based on an instruction from outside, and one bit is outputted every one chip time (obtained by dividing one symbol time by the number of chips).
The adder 4 adds and outputs signals transmitted from the delay element 5 and multiplier 2.
Moreover, the adder 4 transmits the added signal (correlation value) as a correlation output to the outside when one symbol time elapses after addition is started.
The delay element 5 delays the signal outputted by the adder 4 only by one chip time, returns it to the adder 4 and outputs it.
Specifically, the signal outputted by the multiplier 2 is accumulated/added over one symbol time by operation of adder 4 and delay element 5, so that the correlation output can be obtained after one symbol time elapses.
An operation of the conventional sliding correlator will next be described. The CDMA modulated analog signal is converted to a digital signal by the A/D converter 1, and multiplied by the PN code outputted by the PN code register 3 in the multiplier 2.
Subsequently, the adder 4 adds the signal outputted by the multiplier 2, and the signal returned from the delay element 5 over one symbol time to output the correlation output.
The correlation value for one symbol time is obtained as the correlation output in this manner.
Here, the synchronization phase can be detected as a point at which the correlation output reaches its peak, but when the sliding correlator is used, the correlation output cannot be obtained until one symbol time elapses. Therefore, the correlation output is obtained using each chip as a symbol start point, and the synchronization capture is attained in such a manner that the correlation output peaks. In general, it takes one symbol time multiplied by the number of chips to obtain the peak of the correlation output.
To solve the problem, a plurality of sliding correlators corresponding to the number of chips are arranged in parallel, and the correlation output is computed at a timing deviated by each chip in each sliding correlator. In this method, the synchronization capture is attained in a short time, but a circuit scale is impractically large.
On the other hand, in the conventional despreading circuit, as shown in FIG. 12, a matched filter may be used. FIG. 12 is a block diagram of the despreading circuit using the conventional matched filter.
As shown in FIG. 12, the matched filter is constituted of an A/D converter 11, sample hold circuit 12, multiplying means 13, PN code register 14, and adding means 15.
Each section will be described hereinafter in detail.
The A/D converter 11 receives a CDMA modulated analog signal, converts it to a digital signal of N bits, and outputs it, in the same manner as the A/D converter 1 in the sliding correlator.
Here, in consideration of signal precision, the A/D converter 11 preferably converts the analog signal to the digital signal of about six bits.
The sample hold circuit 12 is formed by connecting flip-flop circuits (D-FF) corresponding to the number of chips per one symbol in multiple stages. Each time the N bit signal is received from the A/D converter 11, the N bit signal transmitted from the previous D-FF is held. Moreover, the present held signal is successively transmitted to the next D-FF, and additionally transmitted to the multiplier 13.
Additionally, the first D-FF holds the N bit signal transmitted from the A/D converter 11, instead of the signal transmitted from the previous D-FF.
Specifically, the sample hold circuit 12 is provided with output terminals corresponding to the oversample multiple of the number of chips per one symbol to successively move the N bit signal transmitted from A/D converter 11 for each chip to the next output terminal and emit an output.
The multiplying means 13 is provided with a plurality of multipliers for the D-FFs of sample hold circuit 12 to multiply the N bit signal transmitted from each associated D-FF and the corresponding PN code transmitted from the PN code register 14 and output the N bit signal.
The PN code register 14 is the same as the PN code register 3 of the sliding correlator, except that the PN code for each chip is transmitted to the associated multiplier of the multiplying means 13.
As shown in FIG. 13, the adding means 15 is provided with a plurality of adders 20a to 20n to add the N bit signal transmitted from the multiplying means 13 and emit the correlation output of N bits. FIG. 13 is a block diagram of adding means 15.
As shown in FIG. 13, the adding means 15 is constituted of a plurality of adders 20 and an adder 23.
Moreover, each adder 20 is constituted of a plurality of adders 21, and flip-flop circuits (D-FF) 22 connected to the adders 21.
Specifically, a first adder 20a adds each two sets of a plurality of N bit signals transmitted from the multiplying means 13 by the adder 21, adjusts a timing by the D-FF 22, and outputs a set of the xc2xd number of N bit signals.
Specifically, as shown in FIGS. 12 and 13, when the number of chips per symbol is 256, the number of N bit signals outputted by the multiplying means 13 is 256 corresponding to the oversample multiple of the chips. Therefore, the number of N bit signals outputted by the first adder 20a is 128 corresponding to half of the oversample multiple of the chips.
Furthermore, a second adder 20b adds each two signals of a plurality of signals transmitted from the first adder 20a by the adder 21, adjusts the timing by D-FF 22, and outputs a set of the xc2xd number of N bit signals.
The set of a plurality of signals transmitted from the multiplying means 13 is successively added/synthesized by the adders 20a to 20n to reduce the signals by half. When two signals remain, the two signals are added by the adder 23 to transmit the correlation output to the outside.
An operation of the despreading circuit using the conventional matched filter will next be described.
The CDMA modulated analog signal is converted to the digital signal by the A/D converter 11, held for each sample by the sample hold circuit 12, successively fed rearward, and transmitted to the multiplying means 13.
Subsequently, the multiplying means 13 receives signal inputs corresponding to the number of samples, multiplies the inputs by the corresponding PN code transmitted from the PN code register 14, and emits an output.
Subsequently, the adding means 15 collectively adds/synthesizes the signals outputted by the multiplying means 13, and transmits the correlation output to the outside.
Additionally, the matched filter is broadly applied in the receiver of the spread spectrum communication, and the prior art regarding the matched filter is described, for example, in xe2x80x9cDigital Matched Filter for Direct Spread Spectrumxe2x80x9d of Japanese Patent Application Laid-open No. 107271/1997.
Moreover, the sliding correlator and matched filter for use in the spread spectrum communication are described in xe2x80x9cDespreading Device and Receiverxe2x80x9d of Japanese Patent Application Laid-open No. 68616/1999.
As described above, in the despreading circuit using the conventional sliding correlator, the number of gates is small, power consumption can be reduced, but much time is disadvantageously required from when the synchronization capture is attained until the correlation output is obtained.
Moreover, in the despreading circuit using the matched filter, since the correlation output is obtained for each phase, the time from when the synchronization capture is attained until the correlation output is obtained is short, but the number of gates is increased in accordance with the number of chips. Accordingly, the power consumption is disadvantageously increased.
The present invention has been developed in consideration of the above circumstances, and an object thereof is to provide a despreading circuit which can reduce a circuit scale and power consumption.
The present invention provides a despreading circuit which comprises a searcher using a matched filter for capturing synchronization to capture the synchronization from high-order one bit or a plurality of small bits of an input signal; and a sliding correlator for, on capturing the synchronization, despreading the input signal to perform demodulation, so that the circuit scale and power consumption can be reduced.
Moreover, the present invention provides a despreading circuit which comprises an A/D converter for receiving a CDMA modulated analog signal and converting it to a digital signal of N bits to emit an output; a searcher for detecting a synchronization phase as a symbol start point of the CDMA modulated analog signal based on a high-order k bit signal of the N bit digital signal outputted by the A/D converter to output phase information as a signal indicating the synchronization phase; a control circuit for outputting a signal for allowing despreading to be performed as a timing for starting the despreading in accordance with the phase information transmitted from the searcher; and a sliding correlator for receiving the signal for allowing the despreading to be performed, and starting the despreading of the N bit digital signal outputted by the A/D converter to output a correlation output for one symbol time as a demodulated signal, so that the circuit scale and power consumption can be reduced.
Furthermore, in the despreading circuit of the present invention, the searcher detects the synchronization phase as the symbol start point of the CDMA modulated analog signal based on a signal of high-order one bit of N bits outputted by the A/D converter, and outputs the phase information as the signal indicating the synchronization phase, so that the circuit scale and power consumption can be reduced.
Moreover, in the despreading circuit of the present invention, the searcher detects a symbol of a direct wave of the CDMA modulated analog signal, and the synchronization phase as a symbol start point of a single or a plurality of delay waves, and outputs a plurality of phase information as signals indicating the synchronization phases of the direct wave and the delay wave. The sliding correlators are provided corresponding to the number of the phase information detected and outputted by the searcher to receive the signal for allowing the despreading to be performed from the control circuit at a timing corresponding to each phase information, start the despreading of the N bit digital signal outputted by the A/D converter and to output the correlation output for one symbol time as the demodulated signal. The control circuit selects the corresponding sliding correlator for the plurality of phase information transmitted from the searcher, and transmits to the selected sliding correlator the signal for allowing the despreading to be performed in accordance with the phase information. The demodulated signal transmitted from each sliding correlator can be RAKE synthesized by adjusting the timing.
Additionally, in the despreading circuit of the present invention, an operation of capturing the synchronization in the searcher is performed intermittently, so that the power consumption can be reduced.
Moreover, in the despreading circuit of the present invention, the searcher comprises a sample hold circuit provided with flip-flop circuits connected in multiple stages in accordance with the number of chips for, on receiving an input of digital signal, successively transmitting the digital signal to the next flip-flop circuit while the digital signal is held in the flip-flop circuit; multiplying means provided with multipliers for the flip-flop circuits of the sample hold circuit for, when the digital signal held by the flip-flop circuit connected to each multiplier is successively transmitted to the next flip-flop circuit, multiplying the digital signal and the corresponding bit of PN code as a separately inputted spread code by each multiplier to emit an output; adding means for collectively adding the digital signals outputted by the multipliers of the multiplying means to output the correlation output; and a PN code register for transmitting the PN code as the spread code to the multiplying means, so that the circuit scale and power consumption can be reduced.
Furthermore, in the despreading circuit of the present invention, the adding means has a plurality of CMOS inverters corresponding to the bits in the digital signals outputted by the multipliers of the multiplying means, to add outputs of the plurality of CMOS inverters and emit an output. The CMOS inverter outputs a voltage of a specific level when a value of the corresponding bit of the digital signals transmitted from the multipliers is xe2x80x9c0xe2x80x9d, and outputs a voltage of a ground level when the bit value is xe2x80x9c1xe2x80x9d, so that the circuit scale and power consumption can be reduced.
Moreover, in the despreading circuit of the present invention, the adding means comprises constant-current supply means for supplying an electric current in accordance with each bit value in the digital signals outputted by the multipliers of the multiplying means; a CMOS inverter provided for each bit in the digital signals outputted by the multipliers of the multiplying means to output a specific positive current when the corresponding bit value of the digital signals is xe2x80x9c0xe2x80x9d and output a specific negative current when the bit value is xe2x80x9c1xe2x80x9d; and output means for converting the electric currents outputted by the plurality of CMOS inverters to voltage signals to emit outputs, so that the circuit scale and power consumption can be reduced.
Furthermore, in the despreading circuit of the present invention, the constant-current supply means is provided with electric current input and output MOS transistors for the CMOS inverters. The MOS transistor is weighted in accordance with each bit in the digital signals outputted by the multipliers of the multiplying means, so that circuit scale and power consumption can be reduced.